This invention relates to a digital integrated circuits, and more specifically to a system for improved delay voltage level shifting.
CMOS-based (complementary metal-oxide semiconductor) integrated circuits operate at a voltage input supplied by voltage rails. Power consumption in the core logic of the integrated circuit may be minimized if low rail voltages are used. The output digital signals of the core logic typically switch between the rail voltage and ground. Sometimes the low rail voltages of the integrated circuit are insufficient to be used as output voltages for a CMOS signal that is sent from the core logic. The output voltage is increased in a level shifting input/output (IO) circuit to facilitate sending the CMOS signal. Previous level shifting IO circuits experience delays and may induce an undesirable DC current path through the circuit.